As solid state electronic display technology moves to smaller scales, formation of interconnects that can address multiple circuit elements independently becomes increasingly challenging. This difficulty is magnified when all interconnects need to be on the same face of the substrate and the morphology needs to be maintained as approximately planar. Conventional approaches for creating interconnects, such as photolithographic techniques have lower bounds on the feature sizes they can produce due to the wavelength of light that is used to expose the resist. Special techniques, such as e-beam lithography and Damascene processes, can be used to create even smaller feature sizes, but they are not universally applicable.
High-density interconnects are generally formed by bridging one conductor over another using a dielectric material to separate the two conductors. However, even bridging interconnects over one another like this is limited by pin-hole density, unacceptably increased parasitic capacitance, and difficulties associated with optically defining fine metal tracks over stepped material. Interconnects with air bridges can be fabricated using sacrificial layers that support interconnects prior to plating and are later removed, but this requires multiple processing steps and results in radically non-planar surfaces.